In an interface standard such as Serial ATA, spread spectrum clocking (which is hereinafter abbreviated to SSC) is defined to reduce EMI (electro magnetic interface) (see, for example, Document 1).
FIG. 17 is a graph showing how a clock frequency varies according to a SSC function in the Serial ATA standard. Moreover, FIG. 18 is an example of a spectrum of a clock signal according to the SSC function in the Serial ATA standard. SSC is a technique of modulating the frequency of a clock signal output from a clock source so as to have a predetermined percentage modulation (for example, δ=0.5%) and a predetermined modulation period (for example, fm=30 kHz to 33 kHz) for spreading the spectrum as shown in FIG. 17, to thereby reduce the peak value of the spectrum as shown in FIG. 18.
An example of a clock generation circuit for realizing a spread spectrum is a circuit including: a PLL circuit for generating clock signals having a plurality of kinds of phases; and a phase interpolation unit for performing a periodic phase shift on the generated clock signals having the plurality of kinds of phases, wherein one clock signal which is to be output is selected from a plurality of kinds of clock signals generated by the phase interpolation unit (for example, see Patent Document 1).
In the clock generation circuit which in this way generates a spread spectrum clock signal, the periodic phase shift is performed out of the PLL circuit. Therefore, if phase variations in the phase shift exist, the variations may directly appear as high frequency jitter in an output. If a data signal including the high frequency jitter is output, a receiving circuit may not be able to receive the data, and thus the connectivity between sets having a Serial ATA may be reduced.
To solve the problem, as shown in FIG. 19, a clock generation circuit may be configured such that a PLL circuit (referred to as a second stage PLL circuit) for receiving the spread spectrum clock signal is further provided so that the high frequency jitter may be reduced by a low-pass filter characteristic of the second stage PLL circuit. In the figure, a frequency modulation circuit for receiving a reference clock signal REFCK and generating a spread spectrum clock signal CK_SSC is denoted by 301. Moreover, the second stage PLL circuit for receiving the clock signal CK_SSC and outputting a clock signal CKOUT is denoted by 302. It is to be noted that the second stage PLL circuit is a general PLL circuit including a phase comparator, a charge pump circuit, a second order LPF (Low Pass Filter), a VCO (voltage-controlled oscillator), and a frequency division circuit. In the clock generation circuit including the second stage PLL circuit, the bandwidth (cut-off frequency) of the second stage PLL circuit is set to be a low bandwidth to reduce the high frequency jitter. Generally, a PLL circuit having a low bandwidth serves as a jitter filter for jitter having a higher frequency component than the bandwidth of an input clock signal.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-184488
Document 1: Serial ATA Workgroup “SATA: High Speed Serialized AT Attachment”, Revision 1.0, 29 Aug. 2001